View HT49R70A-1_308998.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HT49R70A-1/HT49C70-1/HT49C70L 8-Bit LCD Type MCU
Features
* Operating voltage: * Buzzer output * On-chip crystal, RC and 32768Hz crystal oscillator * HALT function and wake-up feature reduce power
fSYS=4MHz: 2.2V~5.5V for HT49R70A-1/HT49C70-1 fSYS=8MHz: 3.3V~5.5V for HT49R70A-1/HT49C70-1 fSYS=500kHz: 1.2V~2.2V for HT49C70L
* 8 input lines * 16 bidirectional I/O lines * Two external interrupt input * One 8-bit and one 16-bit programmable timer/event
consumption
* 16-level subroutine nesting * Bit manipulation instruction * 16-bit table read instruction * Up to 0.5ms instruction cycle with 8MHz system clock
counter with PFD (programmable frequency divider) function
* LCD driver with 412, 413 or 404 segments * 8K16 program memory * 2248 data memory RAM * Real Time Clock (RTC) * 8-bit prescaler for RTC * Watchdog Timer
for HT49R70A-1/HT49C70-1
* Up to 8ms instruction cycle with 500kHz system clock
for HT49C70L
* 63 powerful instructions * All instructions in 1 or 2 machine cycles * Low voltage reset/detector functions for
HT49R70A-1/HT49C70-1
* 100-pin QFP package
General Description
The HT49R70A-1/HT49C70-1/HT49C70L are 8-bit, high performance, RISC architecture microcontroller devices specifically designed for a wide range of LCD applications. The mask version HT49C70-1 and HT49C70L are fully pin and functionally compatible with the OTP version HT49R70A-1 device. The HT49C70L is a low voltage version, with the ability to operate at a minimum power supply of 1.2V, making it suitable for single cell battery applications. The advantages of low power consumption, I/O flexibility, programmable frequency divider, timer functions, oscillator options, HALT and wake-up functions and buzzer driver in addition to a flexible and configurable LCD interface, enhance the versatility of these devices to control a wide range of LCD-based application possibilities such as measuring scales, electronic multimeters, gas meters, timers, calculators, remote controllers and many other LCD-based industrial and home appliance applications.
Rev. 1.30
1
July 24, 2003
HT49R70A-1/HT49C70-1/HT49C70L
Block Diagram
In te rru p t C ir c u it P ro g ra m M e m o ry P ro g ra m C o u n te r STACK IN T C TM R0C TM R0 PFD0 TM R1C TM R1 PFD1 M U X M U X fS fS
YS YS
/4 ut R0 R1 V ase O ut
RTC O P B 2 /T M P B 3 /T M TM R 0O fS Y S T im e B fT 1 D fS M U X
YS
In s tr u c tio n R e g is te r
MP
M U
RTC X DATA M e m o ry W DT T im e B a s e
/4 OSC3 OSC4
RTC
OSC
W DT OSC PC 0~PC7 PORT B P B 0 /IN T 0 P B 1 /IN T 1 P B 2 /T M R 0 P B 3 /T M R 1 PB4~PB7 PORT A PA PA PA PA PA E N /D IS 0 /B Z 1 /B Z 2 3 /P F D 4~PA7
In s tr u c tio n D ecoder ALU T im in g G e n e r a tio n
MUX
PC
STATUS PB
S h ifte r
BP OSC2 OSC4 OS RE VD VS OS S S D C3 L C D D r iv e r C1 ACC LCD M e m o ry PA
H ALT
L V D /L V R C O M 0~ COM2 C O M 3/ SEG 40 SEG 0~ SEG 39
Rev. 1.30
2
July 24, 2003
HT49R70A-1/HT49C70-1/HT49C70L
Pin Assignment
SEG SEG SEG SEG SEG SEG SEG SEG SEG OSC OSC VD OSC OSC RE P A 0 /B P A 1 /B PA P A 3 /P F PA D D S Z Z 1 5 C C C C C 6 7 T0 T1 R0 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 4445 46 4748 49 50 8 7 6 5 4 3 2
100 99 98 97 96 9594 93 92 91 90 89 88 87 86 8584 83 82 81
4 2 1 1 2 3 4 5 6 7 8
80 79 78 77 76 75 74 73 72 71 70 69 68
2
3
4
0
PA N N N N N PA PA PB PB PB2 PB3 0 /IN 1 /IN /T M /T M P P P P P P P P P P P P
R1 B4 B5 B6 B7 C0 C1 C2 C3 C4 C5 C6 C7 NC NC NC NC NC VSS
H T 4 9 R 7 0 A -1 /H T 4 9 C 7 0 -1 /H T 4 9 C 7 0 L 1 0 0 Q F P -A
67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
SEG9 SEG 10 SEG 11 NC NC NC SEG 12 SEG 13 SEG 14 SEG 15 SEG 16 SEG 17 SEG 18 SEG 19 SEG 20 SEG 21 SEG 22 SEG 23 SEG 24 SEG 25 SEG 26 SEG 27 SEG 28 SEG 29 NC NC NC NC NC NC
NC SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG COM COM COM COM C2 C1 V2 V1 VLC D 30 31 32 33 34 35 36 37 38 39 3 /S E G 4 0 2 0 1
Rev. 1.30
3
July 24, 2003
HT49R70A-1/HT49C70-1/HT49C70L
Pad Assignment
HT49R70A-1
P A 3 /P F D
83
P A 0 /B Z
P A 1 /B Z
OSC3
OSC4
OSC1
OSC2
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
VDD
RES
PA2
PA4
1 2 3 5 7 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66 65
PA5 PA6 PA7 P B 0 /IN T 0 P B 1 /IN T 1 P B 2 /T M R 0 P B 3 /T M R 1 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 VSS
SEG8 SEG9 SEG 10 SEG 11 SEG 12 SEG 13 SEG 14 SEG 15 SEG 16 SEG 17 SEG 18 SEG 19 SEG 20 SEG 21 SEG 22 SEG 23 SEG 24 SEG 25 SEG 26 SEG 27 SEG 28 SEG 29
4 6 8
TEST3 TEST2 TEST1
64 63 62 61 60 59 58 57
(0 , 0 )
56 55 54 53 52 51 50 49 48 47 46 45
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
* The IC substrate should be connected to VSS in the PCB layout artwork.
VLCD
V1
V2
C1
C2
COM0
COM1
COM2
SEG 35
SEG 34
SEG 33
SEG 32
SEG 31
SEG 30
C O M 3 /S E G 4 0
SEG 39
SEG 38
SEG 37
SEG 36
Rev. 1.30
4
July 24, 2003
HT49R70A-1/HT49C70-1/HT49C70L
HT49C70-1
P A 3 /P F D 83 P A 0 /B Z P A 1 /B Z
OSC3
OSC4
OSC1
OSC2
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
VDD
RES
PA2
PA4 1 PA5 PA6 PA7 P B 0 /IN T 0 P B 1 /IN T 1 6 8 10 12 13 14 15 16 17 18 19 20 21 22 23 24 25 VLCD 26 P B 2 /T M R 0 P B 3 /T M R 1 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 VSS 4 5 3 2
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65 64 63 62 61 SEG9 SEG 10 SEG 11 SEG 12 SEG 13 SEG 14 SEG 15 SEG 16 SEG 17 SEG 18 SEG 19 SEG 20 SEG 21 SEG 22 SEG 23 SEG 24 SEG 25 SEG 26 SEG 27 SEG 28 SEG 29
7 9
TEST3 TEST2
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45
11 TEST1
(0 , 0 )
27 V2
28 C1
29 C2
30 COM0
31
32
33
34
35
36
37
38
39
40
41
42
43
44
SEG 35
SEG 34
SEG 33
SEG 32
SEG 31
SEG 30
* The IC substrate should be connected to VSS in the PCB layout artwork.
V1
COM1
COM2
C O M 3 /S E G 4 0
SEG 39
SEG 38
SEG 37
SEG 36
Rev. 1.30
5
July 24, 2003
HT49R70A-1/HT49C70-1/HT49C70L
HT49C70L
P A 3 /P F D
80
P A 1 /B Z
78
P A 0 /B Z
OSC4
OSC3
OSC2
OSC1
SEG0
SEG1
SEG2
SEG3
SEG5 SEG4
SEG6
SEG8 SEG7
VDD
RES
PA2
79
77
76
70 75 74 73 72 71
69
68
67
66
65
64
63
62
PA4
1
PA5
2 3 4 5
61 60 59 58 6 57 56 55 8 54 53 52 51 50 49 48 47 46 45 44 43 42 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41
PA6 PA7 P B 0 /IN T 0 P B 1 /IN T 1 P B 2 /T M R 0
7 9
SEG9 SEG 10 SEG 11 SEG 12 SEG 13 SEG 14 SEG 15 SEG 16 SEG 17 SEG 18 SEG 19 SEG 20 SEG 21 SEG 22 SEG 23 SEG 24 SEG 25 SEG 26 SEG 27 SEG 28
P B 3 /T M R 1 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 VSS
10 11 12 13 14 15 16 17 18 19 20 21
(0 ,0 )
V2
C1
C2
SEG 38 SEG 39
SEG 36 SEG 37
SEG 35
SEG 34
SEG 33
SEG 32
SEG 31
SEG 30
SEG 29
VCCA1
COM1 COM0
COM2
COM3
* The IC substrate should be connected to VSS in the PCB layout artwork.
VLCD
Rev. 1.30
6
July 24, 2003
HT49R70A-1/HT49C70-1/HT49C70L
Pad Description
Pad Name PA0/BZ PA1/BZ PA2 PA3/PFD PA4~PA7 PB0/INT0 PB1/INT1 PB2/TMR0 PB3/TMR1 PB4~PB7 I/O Options Wake-up Pull-high or None CMOS or NMOS Description PA0~PA7 constitute an 8-bit bidirectional input/output port with Schmitt trigger input capability. Each bit on port can be configured as wake-up input by options. PA0~PA3 can be configured as CMOS output or NMOS input/output with or without pull-high resistor by options. PA4~PA7 are always pull-high NMOS input/output. Of the eight bits, PA0~PA1 can be set as I/O pins or buzzer outputs by options. PA3 can be set as an I/O pin or as a PFD output also by options. PB0~PB7 constitute an 8-bit Schmitt trigger input port. Each bit on port are with pull-high resistor. Of the eight bits, PB0 and PB1 can be set as input pins or as external interrupt control pins (INT0) and (INT1) respectively, by software application. PB2 and PB3 can be set as an input pin or as a timer/event counter input pin TMR0 and TMR1 also by software application. PC0~PC7 constitute an 8-bit bidirectional input/output port with Schmitt trigger input capability. On the port, such can be configured as CMOS output or NMOS input/output with or without pull-high resistor by options. Voltage pump for HT49R70A-1/HT49C70-1. LCD power supply for HT49C70L. LCD power supply for HT49R70A-1/HT49C70-1. Voltage pump for HT49C70L. Voltage pump SEG40 can be set as a segment or as a common output driver for LCD panel by options. COM0~COM2 are outputs for LCD panel plate. LCD driver outputs for LCD panel segments OSC1 and OSC2 are connected to an RC network or a crystal (by options) for the internal system clock. In the case of RC operation, OSC2 is the output terminal for 1/4 system clock. The system clock may come from the RTC oscillator. If the system clock comes from RTCOSC, these two pins can be floating. Real time clock oscillators. OSC3 and OSC4 are connected to a 32768Hz crystal oscillator for timing purposes or to a system clock source (depending on the options). No built-in capacitor Positive power supply Negative power supply, ground Schmitt trigger reset input, active low
I/O
I
3/4
PC0~PC7
I/O
Pull-high or None CMOS or NMOS 3/4 3/4 3/4 1/2, 1/3 or 1/4 Duty 3/4
V2 VLCD V1, C1, C2 COM0~COM2 COM3/SEG40 SEG0~SEG39
I I I O O
OSC1 OSC2
O I
Crystal or RC
OSC3 OSC4 VDD VSS RES
O I 3/4 3/4 I
RTC or System Clock 3/4 3/4 3/4
Absolute Maximum Ratings
Supply Voltage..........................VSS-0.3V to VSS+6.0V* Storage Temperature ............................-50C to 125C Operating Temperature ...........................-40C to 85C Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. * For HT49R70A-1/HT49C70-1 ** For HT49C70L Supply Voltage ........................VSS-0.3V to VSS+2.5V** Input Voltage..............................VSS-0.3V to VDD+0.3V
Rev. 1.30
7
July 24, 2003
HT49R70A-1/HT49C70-1/HT49C70L
D.C. Characteristics
VDD=1.5V for HT49C70L, VDD=3V & VDD=5V for HT49R70A-1 and HT49C70-1 Test Conditions Symbol Parameter VDD Conditions For HT49C70L VDD Operating Voltage 3/4 LVR disable, fSYS=4MHz (for HT49R70A-1/HT49C70-1) fSYS=8MHz (for HT49R70A-1/HT49C70-1) 1.5V No load, fSYS=455kHz IDD1 Operating Current (Crystal OSC) 3V 5V 1.5V No load, fSYS=400kHz IDD2 Operating Current (RC OSC) Operating Current (RC OSC, Crystal) Operating Current (fSYS=32768Hz) 3V 5V IDD3 5V 1.5V IDD4 3V 5V 1.5V ISTB1 Standby Current (*fS=T1) 3V 5V 1.5V ISTB2 Standby Current (*fS=32.768kHz OSC) 3V 5V 1.5V ISTB3 Standby Current (*fS=WDT RC OSC) 3V 5V ISTB4 Standby Current (*fS=32.768kHz OSC) Standby Current (*fS=32.768kHz OSC) Standby Current (*fS=WDT RC OSC) Standby Current (*fS=WDT RC OSC) Input Low Voltage for I/O Ports, TMR and INT 3V 5V 3V 5V 3V 5V 3V 5V 3/4 No load, system HALT, LCD On at HALT, R type, 1/2 bias No load, system HALT, LCD On at HALT, R type, 1/3 bias No load, system HALT, LCD On at HALT, R type, 1/2 bias No load, system HALT, LCD On at HALT, R type, 1/3 bias 3/4 No load, system HALT LCD On at HALT, C type No load, system HALT, LCD On at HALT, C type No load, system HALT, LCD Off at HALT No load No load, fSYS=8MHz No load, fSYS=4MHz No load, fSYS=4MHz 1.2 2.2 3.3 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 0 3/4 3/4 3/4 60 1 3 50 1 3 3 2.5 0.3 0.6 0.1 3/4 3/4 1 2.5 10 0.5 2 6 17 34 13 28 14 26 10 19 3/4 2.2 5.5 5.5 100 2 5 100 2 5 5 5 0.6 1 0.5 1 2 2 5 20 1 5 10 30 60 25 50 25 50 20 40 0.3VDD V V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA V Min. Typ. Max. Unit Ta=25C
ISTB5
ISTB6
ISTB7
VIL1
Rev. 1.30
8
July 24, 2003
HT49R70A-1/HT49C70-1/HT49C70L
Test Conditions Symbol Parameter VDD 1.5V VIH1 Input High Voltage for I/O Ports, TMR and INT Input Low Voltage (RES) Input High Voltage (RES) 3V 5V VIL2 VIH2 3/4 3/4 1.5V IOL1 I/O Port Sink Current 3V 5V 1.5V IOH1 I/O Port Source Current 3V 5V IOL2 LCD Common and Segment Current LCD Common and Segment Current 3V 5V 3V 5V 1.5V RPH Pull-high Resistance of I/O 3V Ports and INT0, INT1 5V Low Voltage Reset Voltage Low Voltage Detector Voltage tSYS=1/fSYS *fS please refer to the WDT clock option 3/4 3/4 3/4 VOH=0.9VDD VOL=0.1VDD VOH=0.9VDD VOL=0.1VDD 3/4 3/4 3/4 Conditions 0.8VDD 0.7VDD 0.7VDD 0 0.9VDD 0.4 6 10 -0.3 -2 -5 210 350 -80 -180 75 40 10 3/4 2.7 3.0 3/4 3/4 3/4 3/4 3/4 0.8 12 25 -0.6 -4 -8 420 700 -160 -360 150 60 30 3.2 3.3 VDD VDD VDD 0.4VDD VDD 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 300 80 50 3.6 3.6 V V V V V mA mA mA mA mA mA mA mA mA mA kW kW kW V V Min. Typ. Max. Unit
IOH2
VLVR VLVD Note:
Rev. 1.30
9
July 24, 2003
HT49R70A-1/HT49C70-1/HT49C70L
A.C. Characteristics
VDD=1.5V for HT49C70L, VDD=3V & VDD=5V for HT49R70A-1 and HT49C70-1 Test Conditions Symbol Parameter VDD 3/4 fSYS1 System Clock (Crystal OSC) 3/4 3/4 3/4 fSYS2 System Clock (RC OSC) System Clock (32768Hz Crystal OSC) RTC Frequency 3/4 3/4 fSYS3 fRTCOSC 3/4 3/4 3/4 fTIMER Timer I/P Frequency 3/4 3/4 1.5V tWDTOSC Watchdog Oscillator Period 3V 5V tRES tSST tINT Note: External Reset Low Pulse Width System Start-up Timer Period Interrupt Pulse Width *tSYS= 1/fSYS 3/4 3/4 3/4 For HT49C70L For HT49R70A-1/HT49C70-1 Wake-up from HALT For HT49C70L For HT49R70A-1/HT49C70-1 3/4 1.2V~2.2V 2.2V~5.5V 3.3V~5.5V Conditions 1.2V~2.2V 2.2V~5.5V 3.3V~5.5V 1.2V~2.2V 2.2V~5.5V 3.3V~5.5V 3/4 3/4 400 400 400 400 400 400 3/4 3/4 0 0 0 35 45 32 10 1 3/4 10 1 3/4 3/4 3/4 3/4 3/4 3/4 32768 32768 3/4 3/4 3/4 70 90 65 3/4 3/4 1024 3/4 3/4 500 4000 8000 500 4000 8000 3/4 3/4 500 4000 8000 140 180 130 3/4 3/4 3/4 3/4 3/4 kHz kHz kHz kHz kHz kHz Hz Hz kHz kHz kHz ms ms ms ms ms *tSYS ms ms Min. Typ. Max. Unit Ta=25C
Rev. 1.30
10
July 24, 2003
HT49R70A-1/HT49C70-1/HT49C70L
Functional Description
Execution Flow The system clock is derived from either a crystal or an RC oscillator or a 32768Hz crystal oscillator. It is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle. The pipelining scheme makes it possible for each instruction to be effectively executed in a cycle. If an instruction changes the value of the program counter, two cycles are required to complete the instruction. Program Counter - PC The program counter (PC) is 13 bits wide and it controls the sequence in which the instructions stored in the program ROM are executed. The contents of the PC can specify a maximum of 8192 addresses. After accessing a program memory word to fetch an instruction code, the value of the PC is incremented by 1. The PC then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip execution, loading a PCL register, a subroutine call, an initial reset, an internal interrupt, an external interrupt, or returning from a subroutine, the PC manipulates the program transfer by loading the address corresponding to each instruction. The conditional skip is activated by instructions. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get a proper instruction; otherwise proceed to the next instruction. The lower byte of the PC (PCL) is a readable and writeable register (06H). Moving data into the PCL performs a short jump. The destination is within 256 locations.
T2 T3 T4 T1 T2 T3 T4
S y s te m O S C 2 (R C
C lo c k o n ly ) PC
T1
T2
T3
T4
T1
PC
PC+1
PC+2
F e tc h IN S T (P C ) E x e c u te IN S T (P C -1 )
F e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 )
Execution Flow Program Counter *12 0 0 0 0 0 0 0 *12 #12 *11 0 0 0 0 0 0 0 *11 #11 *10 0 0 0 0 0 0 0 *10 #10 *9 0 0 0 0 0 0 0 *9 #9 S9 *8 0 0 0 0 0 0 0 *8 #8 S8 *7 0 0 0 0 0 0 0 @7 #7 S7 *6 0 0 0 0 0 0 0 PC+2 @6 #6 S6 @5 #5 S5 @4 #4 S4 @3 #3 S3 @2 #2 S2 @1 #1 S1 @0 #0 S0 *5 0 0 0 0 0 0 0 *4 0 0 0 0 1 1 1 *3 0 0 1 1 0 0 1 *2 0 1 0 1 0 1 0 *1 0 0 0 0 0 0 0 *0 0 0 0 0 0 0 0
Mode Initial Reset External Interrupt 0 External Interrupt 1 Timer/Event Counter 0 overflow Timer/Event Counter 1 overflow Time Base Interrupt RTC Interrupt Skip Loading PCL Jump, Call Branch Return From Subroutine
S12 S11 S10
Program Counter Note: *12~*0: Program counter bits #12~#0: Instruction code bits S12~S0: Stack register bits @7~@0: PCL bits
Rev. 1.30
11
July 24, 2003
HT49R70A-1/HT49C70-1/HT49C70L
When a control transfer takes place, an additional dummy cycle is required. Program Memory - ROM The program memory is used to store the program instructions which are to be executed. It also contains data, table, and interrupt entries, and is organized into 819216 bits which are addressed by the PC and table pointer. Certain locations in the ROM are reserved for special usage:
* Location 000H
n00H nFFH 000H 004H 008H 00C H 010H 014H 018H D e v ic e in itia liz a tio n p r o g r a m E x te r n a l in te r r u p t 0 s u b r o u tin e E x te r n a l in te r r u p t 1 s u b r o u tin e T im e r /e v e n t c o u n te r 0 in te r r u p t s u b r o u tin e T im e r /e v e n t c o u n te r 1 in te r r u p t s u b r o u tin e T im e B a s e In te r r u p t R T C In te rru p t P ro g ra m ROM
Location 000H is reserved for program initialization. After chip reset, the program always begins execution at this location.
* Location 004H
L o o k - u p ta b le ( 2 5 6 w o r d s )
1FFFH
L o o k - u p ta b le ( 2 5 6 w o r d s ) 1 6 b its N o te : n ra n g e s fro m 0 to 1 F
Location 004H is reserved for the external interrupt service program. If the INT0 input pin is activated, and the interrupt is enabled, and the stack is not full, the program begins execution at location 004H.
* Location 008H
Program Memory
* Table location
Location 008H is reserved for the external interrupt service program also. If the INT1 input pin is activated, and the interrupt is enabled, and the stack is not full, the program begins execution at location 008H.
* Location 00CH
Location 00CH is reserved for the Timer/Event Counter 0 interrupt service program. If a timer interrupt results from a Timer/Event Counter 0 overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 00CH.
* Location 010H
Location 010H is reserved for the Timer/Event Counter 1 interrupt service program. If a timer interrupt results from a Timer/Event Counter 1 overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 010H.
* Location 014H
Any location in the ROM can be used as a look-up table. The instructions TABRDC [m] (the current page, 1 page=256 words) and TABRDL [m] (the last page) transfer the contents of the lower-order byte to the specified data memory, and the contents of the higher-order byte to TBLH (Table Higher-order byte register) (08H). Only the destination of the lower-order byte in the table is well-defined; the other bits of the table word are all transferred to the lower portion of TBLH. The TBLH is read only, and the table pointer (TBLP) is a read/write register (07H), indicating the table location. Before accessing the table, the location should be placed in TBLP. All the table related instructions require 2 cycles to complete the operation. These areas may function as a normal ROM depending upon the users requirements. Stack Register - STACK The stack register is a special part of the memory used to save the contents of the PC. The stack is organized into 16 levels and is neither part of the data nor part of the program, and is neither readable nor writeable. Its activated level is indexed by a stack pointer (SP) and is neither readable nor writeable. At the start of a subroutine call or an interrupt acknowledgment, the contents of the PC is pushed onto the stack. At the end of the subTable Location
Location 014H is reserved for the Time Base interrupt service program. If a Time Base interrupt occurs, and the interrupt is enabled, and the stack is not full, the program begins execution at location 014H.
* Location 018H
Location 018H is reserved for the real time clock interrupt service program. If a real time clock interrupt occurs, and the interrupt is enabled, and the stack is not full, the program begins execution at location 018H. Instruction(s) TABRDC [m] TABRDL [m]
*12 P12 1
*11 P11 1
*10 P10 1
*9 P9 1
*8 P8 1
*7 @7 @7
*6 @6 @6
*5 @5 @5
*4 @4 @4
*3 @3 @3
*2 @2 @2
*1 @1 @1
*0 @0 @0
Table Location Note: *12~*0: Table location bits @7~@0: Table pointer bits P12~P8: Current program counter bits
Rev. 1.30
12
July 24, 2003
HT49R70A-1/HT49C70-1/HT49C70L
routine or interrupt routine, signaled by a return instruction (RET or RETI), the contents of the PC is restored to its previous value from the stack. After chip reset, the SP will point to the top of the stack. If the stack is full and a non-masked interrupt takes place, the interrupt request flag is recorded but the acknowledgment is still inhibited. Once the SP is decremented (by RET or RETI), the interrupt is serviced. This feature prevents stack overflow, allowing the programmer to use the structure easily. Likewise, if the stack is full, and a CALL is subsequently executed, a stack overflow occurs and the first entry is lost (only the most recent 16 return addresses are stored). Data Memory - RAM The data memory (RAM) is designed with 2458 bits, and is divided into two functional groups, namely; special function registers and general purpose data memory, most of which are readable/writeable, although some are read only. Of the two types of functional groups, the special function registers consist of an Indirect addressing register 0 (00H), a Memory pointer register 0 (MP0;01H), an Indirect addressing register 1 (02H), a Memory pointer register 1 (MP1;03H), a Bank pointer (BP;04H), an A c c u m u l at or ( A C C ; 0 5 H ) , a P r ogr a m co u n t e r lower-order byte register (PCL;06H), a Table pointer (TBLP;07H), a Table higher-order byte register (TBLH;08H), a Real time clock control register (RTCC;09H), a Status register (STATUS;0AH), an Interrupt control register 0 (INTC0;0BH), a Timer/Event Counter 0 (TMR0;0DH), a Timer/Event Counter 0 control register (TMR0C;0EH), a Timer/Event Counter 1 (TMR1H:0FH;TMR1L;10H), a Timer/Event Counter 1 control register (TMR1C;11H), I/O registers (PA;12H, PB;14H, PC;16H), and Interrupt control register 1 (INTC1;1EH). On the other hand, the general purpose data memory, addressed from 20H to FFH, is used for data and control information under instruction commands. The areas in the RAM can directly handle arithmetic, logic, increment, decrement, and rotate operations. Except some dedicated bits, each bit in the RAM can be set and reset by SET [m].i and CLR [m].i They are also indirectly accessible through the Memory pointer register 0 (MP0;01H) or the Memory pointer register 1 (MP1;03H). Indirect Addressing Register Location 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write operation of [00H] and [02H] accesses the RAM pointed to by MP0 (01H) and MP1(03H) respectively. Reading location 00H or 02H indirectly returns the result 00H. While, writing it indirectly leads to no operation.
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0C H 0D H 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1C H 1D H 1EH 1FH 20H
IN T C 1 In d ir e c t A d d r e s s in g R e g is te r 0
MP0 In d ir e c t A d d r e s s in g R e g is te r 1 MP1 BP ACC PCL TBLP TBLH RTCC STATUS IN T C 0 TM R0 TM R0C TM R1H TM R1L TM R1C PA PB PC
S p e c ia l P u r p o s e DATA M EM ORY
:U nused.
R e a d a s "0 "
G e n e ra l P u rp o s e DATA M EM ORY (2 2 4 B y te s ) FFH
RAM Mapping The function of data movement between two indirect addressing registers is not supported. The memory pointer registers, MP0 and MP1, are both 8-bit registers used to access the RAM by combining corresponding indirect addressing registers. MP0 can only be applied to data memory, while MP1 can be applied to data memory and LCD display memory. Accumulator - ACC The accumulator (ACC) is related to the ALU operations. It is also mapped to location 05H of the RAM and is capable of operating with immediate data. The data movement between two data memory locations must pass through the ACC.
Rev. 1.30
13
July 24, 2003
HT49R70A-1/HT49C70-1/HT49C70L
Arithmetic and Logic Unit - ALU This circuit performs 8-bit arithmetic and logic operations and provides the following functions:
* Arithmetic operations (ADD, ADC, SUB, SBC, DAA) * Logic operations (AND, OR, XOR, CPL) * Rotation (RL, RR, RLC, RRC) * Increment and Decrement (INC, DEC) * Branch decision (SZ, SNZ, SIZ, SDZ etc.)
Interrupts The device provides two external interrupts, two internal timer/event counter interrupts, an internal time base interrupt, and an internal real time clock interrupt. The interrupt control register 0 (INTC0;0BH) and interrupt control register 1 (INTC1;1EH) both contain the interrupt control bits that are used to set the enable/disable status and interrupt request flags. Once an interrupt subroutine is serviced, other interrupts are all blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may take place during this interval, but only the interrupt request flag will be recorded. If a certain interrupt requires servicing within the service routine, the EMI bit and the corresponding bit of the INTC0 or of INTC1 may be set in order to allow interrupt nesting. Once the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack should be prevented from becoming full. All these interrupts can support a wake-up function. As an interrupt is serviced, a control transfer occurs by pushing the contents of the PC onto the stack followed by a branch to a subroutine at the specified location in the ROM. Only the contents of the PC is pushed onto the stack. If the contents of the register or of the status register (STATUS) is altered by the interrupt service program which corrupts the desired control sequence, the contents should be saved in advance. External interrupts are triggered by a high to low transition of INT0 or INT1, and the related interrupt request flag (EIF0; bit 4 of INTC0, EIF1; bit 5 of INTC0) is set as well. After the interrupt is enabled, the stack is not full, and the external interrupt is active, a subroutine call to location 04H or 08H occurs. The interrupt request flag (EIF0 or EIF1) and EMI bits are all cleared to disable other interrupts. Function
The ALU not only saves the results of a data operation but also changes the status register. Status Register - STATUS The status register (0AH) is 8 bits wide and contains, a carry flag (C), an auxiliary carry flag (AC), a zero flag (Z), an overflow flag (OV), a power down flag (PD), and a watchdog time-out flag (TO). It also records the status information and controls the operation sequence. Except for the TO and PD flags, bits in the status register can be altered by instructions similar to other registers. Data written into the status register does not alter the TO or PD flags. Operations related to the status register, however, may yield different results from those intended. The TO and PD flags can only be changed by a Watchdog Timer overflow, chip power-up, or clearing the Watchdog Timer and executing the HALT instruction. The Z, OV, AC, and C flags reflect the status of the latest operations. On entering the interrupt sequence or executing the subroutine call, the status register will not be automatically pushed onto the stack. If the contents of the status is important, and if the subroutine is likely to corrupt the status register, the programmer should take precautions and save it properly.
Labels C
Bits 0
C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared. OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. PD is cleared by either a system power-up or executing the CLR WDT instruction. PD is set by executing the HALT instruction. TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is set by a WDT time-out. Unused bit, read as 0 Status Register
AC Z OV PD TO 3/4
1 2 3 4 5 6, 7
Rev. 1.30
14
July 24, 2003
HT49R70A-1/HT49C70-1/HT49C70L
The internal Timer/Event Counter 0 interrupt is initialized by setting the Timer/Event Counter 0 interrupt request flag (T0F;bit 6 of INTC0), which is normally caused by a timer overflow. After the interrupt is enabled, and the stack is not full, and the T0F bit is set, a subroutine call to location 0CH occurs. The related interrupt request flag (T0F) is reset, and the EMI bit is cleared to disable further interrupts. The Timer/Event Counter 1 is operated in the same manner but its related interrupt request flag is T1F (bit 4 of INTC1) and its subroutine call location is 10H. The time base interrupt is initialized by setting the time base interrupt request flag (TBF;bit 5 of INTC1), that is caused by a regular time base signal. After the interrupt is enabled, and the stack is not full, and the TBF bit is set, a subroutine call to location 14H occurs. The related interrupt request flag (TBF) is reset and the EMI bit is cleared to disable further interrupts. The real time clock interrupt is initialized by setting the real time clock interrupt request flag (RTF; bit 6 of INTC1), that is caused by a regular real time clock signal. After the interrupt is enabled, and the stack is not full, and the RTF bit is set, a subroutine call to location 18H occurs. The related interrupt request flag (RTF) is reset and the EMI bit is cleared to disable further interrupts. During the execution of an interrupt subroutine, other interrupt acknowledgments are all held until the RETI instruction is executed or the EMI bit and the related interrupt control bit are set both to 1 (if the stack is not full). To return from the interrupt subroutine, RET or RETI Register Bit No. 0 1 2 INTC0 (0BH) 3 4 5 6 7 0 1 2 INTC1 (1EH) 3 4 5 6 7 Label EMI EEI0 EEI1 ET0I EIF0 EIF1 T0F 3/4 ET1I ETBI ERTI 3/4 T1F TBF RTF 3/4 may be invoked. RETI sets the EMI bit and enables an interrupt service, but RET does not. Interrupts occurring in the interval between the rising edges of two consecutive T2 pulses are serviced on the latter of the two T2 pulses if the corresponding interrupts are enabled. In the case of simultaneous requests, the priorities in the following table apply. These can be masked by resetting the EMI bit. Interrupt Source External interrupt 0 External interrupt 1 Timer/Event Counter 0 overflow Timer/Event Counter 1 overflow Time base interrupt Real time clock interrupt Priority 1 2 3 4 5 6 Vector 04H 08H 0CH 10H 14H 18H
The Timer/Event Counter 0 interrupt request flag, T0F, external interrupt 1 request flag (EIF1), external interrupt 0 request flag (EIF0), enable Timer/Event Counter 0 interrupt bit (ET0I), enable external interrupt 1 bit (EEI1), enable external interrupt 0 bit (EEI0), and enable master interrupt bit (EMI) make up of the Interrupt Control register 0 (INTC0) which is located at 0BH in the RAM. The real time clock interrupt request flag (RTF), time base interrupt request flag (TBF), Timer/Event Counter 1 interrupt request flag (T1F), enable real time clock interrupt bit (ERTI), and enable time base interrupt bit (ETBI), enable Timer/Event Counter 1 interrupt bit (ET1I) on the other hand, constitute the Interrupt Control register 1 (INTC1) which is located at 1EH in the RAM. Function
Controls the master (global) interrupt (1=enabled; 0=disabled) Controls the external interrupt 0 (1=enabled; 0=disabled) Controls the external interrupt 1 (1=enabled; 0=disabled) Controls the Timer/Event Counter 0 interrupt (1=enabled; 0=disabled) External interrupt 0 request flag (1=active; 0=inactive) External interrupt 1 request flag (1=active; 0=inactive) Internal Timer/Event Counter 0 request flag (1=active; 0=inactive) Unused bit, read as 0 Controls the Timer/Event Counter 1 interrupt (1=enabled; 0=disabled) Controls the time base interrupt (1=enabled; 0:disabled) Controls the real time clock interrupt (1=enabled; 0:disabled) Unused bit, read as 0 Internal Timer/Event Counter 1 request flag (1=active; 0=inactive) Time base request flag (1=active; 0=inactive) Real time clock request flag (1=active; 0=inactive) Unused bit, read as 0 INTC Register
Rev. 1.30
15
July 24, 2003
HT49R70A-1/HT49C70-1/HT49C70L
EMI, EEI0, EEI1, ET0I, ET1I, ETBI, and ERTI are all used to control the enable/disable status of interrupts. These bits prevent the requested interrupt from being serviced. Once the interrupt request flags (RTF, TBF, T0F, T1F, EIF1, EIF0) are all set, they remain in the INTC1 or INTC0 respectively until the interrupts are serviced or cleared by a software instruction. It is recommended that a program should not use the CALL subroutine within the interrupt subroutine. Its because interrupts often occur in an unpredictable manner or require to be serviced immediately in some applications. During that period, if only one stack is left, and enabling the interrupt is not well controlled, operation of the call in the interrupt subroutine may damage the original control sequence. Oscillator Configuration These devices provide three oscillator circuits for system clocks, i.e., RC oscillator, crystal oscillator and 32768Hz crystal oscillator, determined by options. No matter what type of oscillator is selected, the signal is used for the system clock. The HALT mode stops the system oscillator (RC and crystal oscillator only) and ignores external signal in order to conserve power. The 32768Hz crystal oscillator (system oscillator) still runs at HALT mode. If the 32768Hz crystal oscillator is selected as the system oscillator, the system oscillator is not stopped; but the instruction execution is stopped. Since the system oscillator or oscillator) is also designed for timing purposes, the internal timing (RTC, time base, WDT) operation still runs even if the system enters the HALT mode. Of the three oscillators, if the RC oscillator is used, an external resistor between OSC1 and VSS is required, and the range of the resistance should be from 24kW to 1MW for HT49R70A-1/HT49C70-1 and from 560kW to 1MW for HT49C70L. The system clock, divided by 4, is available on OSC2 with pull-high resistor, which can be used to synchronize external logic. The RC oscillator provides the most cost effective solution. However, the frequency of the oscillation may vary with VDD, temperature, and the chip itself due to process variations. It is therefore, not suitable for timing sensitive operations where accurate oscillator frequency is desired. On the other hand, if the crystal oscillator is selected, a crystal across OSC1 and OSC2 is needed to provide the feedback and phase shift required for the oscillator, and no other external components are required. A resonator may be connected between OSC1 and OSC2 to replace the crystal and to get a frequency reference, but two external capacitors in OSC1 and OSC2 are required. There is another oscillator circuit designed for the real time clock. In this case, only the 32.768kHz crystal oscillator can be applied. The crystal should be connected between OSC3 and OSC4. The RTC oscillator circuit can be controlled to oscillate quickly by setting the QOSC bit (bit 4 of RTCC). It is recommended to turn on the quick oscillating function upon power on, and then turn it off after 2 seconds. The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Although the system enters the power down mode, the system clock stops, and the WDT oscillator still works with a period of approximately 78ms. The WDT oscillator can be disabled by options to conserve power. Watchdog Timer - WDT The WDT clock source is implemented by a dedicated RC oscillator (WDT oscillator) or an instruction clock (system clock/4) or a real time clock oscillator (RTC oscillator). The timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. The WDT can be disabled by options. But if the WDT is disabled, all executions related to the WDT lead to no operation. The WDT time-out period is fS/215~fS/216. If the WDT clock source chooses the internal WDT oscillator, the time-out period may vary with temperature, VDD, and process variations. On the other hand, if the clock source selects the instruction clock and the HALT instruction is executed, WDT may stop counting and lose its protecting purpose, and the logic can only be restarted by an external logic. When the device operates in a noisy environment, using the on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT can stop the system clock.
V
DD
OSC3
OSC1
470pF V OSC1
DD
OSC4
OSC2 C r y s ta l O s c illa to r
fS
YS
/4
OSC2 RC O s c illa to r
3 2 7 6 8 H z C r y s ta l/ R T C O s c illa to r
System Oscillator Rev. 1.30 16 July 24, 2003
HT49R70A-1/HT49C70-1/HT49C70L
S y s te m C lo c k /4 O p tio n S e le c t fS D iv id e r D iv id e r CK R W D T C le a r T CK R T
RTC O SC 32768H z W DT 12kH z OSC
T im e - o u t R e s e t fS /2
15
~ fS /2
16
Watchdog Timer The WDT overflow under normal operation initializes a chip reset and sets the status bit TO. In the HALT mode, the overflow initializes a warm reset, and only the PC and SP are reset to zero. To clear the contents of the WDT, there are three methods to be adopted, i.e., external reset (a low level to RES), software instruction, and a HALT instruction. There are two types of software instructions; CLR WDT and the other set - CLR WDT1 and CLR WDT2. Of these two types of instruction, only one type of instruction can be active at a time depending on the options - CLR WDT times selection option. If the CLR WDT is selected (i.e., CLR WDT times equal one), any execution of the CLR WDT instruction clears the WDT. In the case that CLR WDT1 and CLR WDT2 are chosen (i.e., CLR WDT times equal two), these two instructions have to be executed to clear the WDT; otherwise, the WDT may reset the chip due to time-out. Multi-function Timer These devices provide a multi-function timer for the WDT , time base and RTC but with different time-out periods. The multi-function timer consists of an 8-stage divider and a 7-bit prescaler, with the clock source coming from the WDT OSC or RTC OSC or the instruction clock (i.e., system clock divided by 4). The multi-function timer also provides a selectable frequency signal (ranges
fs D iv id e r
from fS/22 to fS/28) for LCD driver circuits, and a selectable frequency signal (ranging from fS/22 to fS/29) for the buzzer output by options. It is recommended to select a nearly 4kHz signal for the LCD driver circuits to have proper display. Time Base The time base offers a periodic time-out period to generate a regular internal interrupt. Its time-out period ranges from fS/212 to fS/215 selected by options. If time base time-out occurs, the related interrupt request flag (TBF; bit 5 of INTC1) is set. But if the interrupt is enabled, and the stack is not full, a subroutine call to location 14H occurs. The time base time-out signal can also be applied as a clock source of the Timer/Event Counter 1 so as to get a longer time-out period. Real Time Clock - RTC The real time clock (RTC) is operated in the same manner as the time base that is used to supply a regular internal interrupt. Its time-out period ranges from fS/28 to fS/215 by software programming . Writing data to RT2, RT1 and RT0 (bit 2, 1, 0 of RTCC;09H) yields various time-out periods. If the RTC time-out occurs, the related interrupt request flag (RTF; bit 6 of INTC1) is set. But if the interrupt is enabled, and the stack is not full, a subroutine call to location 18H occurs. The real time clock
P r e s c a le r
O p tio n
O p tio n
L C D D r iv e r ( fS /2 2 ~ fS /2 8 ) B u z z e r (fS /2 2~ fS /2 9)
T im e B a s e In te r r u p t fS /2 12~ fS /2 15
Time Base
fS D iv id e r RT2 RT1 RT0 P r e s c a le r
8 to 1 M ux.
fS /2 8~ fS /2 15 R T C In te rru p t
Real Time Clock Rev. 1.30 17 July 24, 2003
HT49R70A-1/HT49C70-1/HT49C70L
time-out signal also can be applied as a clock source of the Timer/Event Counter 0 in order to get a longer time-out period. RT2 0 0 0 0 1 1 1 1 RT1 0 0 1 1 0 0 1 1 RT0 0 1 0 1 0 1 0 1 RTC Clock Divided Factor 2* 2 9* 210* 211* 212 213 214 215 Reset There are three ways in which reset may occur.
* RES is reset during normal operation * RES is reset during HALT * WDT time-out is reset during normal operation
8
When an interrupt request flag is set before entering the HALT status, the system cannot be awakened using that interrupt. If wake-up events occur, it takes 1024 tSYS (system clock period) to resume normal operation. In other words, a dummy period is inserted after the wake-up. If the wake-up results from an interrupt acknowledgment, the actual interrupt subroutine execution is delayed by more than one cycle. However, if the Wake-up results in the next instruction execution, the execution will be performed immediately after the dummy period is finished. To minimize power consumption, all the I/O pins should be carefully managed before entering the HALT status.
Note: * not recommended to be used Power Down Operation - HALT The HALT mode is initialized by the HALT instruction and results in the following.
* The system oscillator turns off but the WDT or RTC
oscillator keeps running (if the WDT oscillator or the real time clock is selected).
* The contents of the on-chip RAM and of the registers
remain unchanged.
* The WDT is cleared and start recounting (if the WDT
clock source is from the WDT oscillator or the real time clock oscillator).
* All I/O ports maintain their original status. * The PD flag is set but the TO flag is cleared. * LCD driver is still running (if the WDT OSC or RTC
The WDT time-out during HALT differs from other chip reset conditions, for it can perform a warm reset that resets only the PC and SP and leaves the other circuits at their original state. Some registers remain unaffected during any other reset conditions. Most registers are reset to the initial condition once the reset conditions are met. Examining the PD and TO flags, the program can distinguish between different chip resets. TO 0 u 0 1 1 PD 0 u 1 u 1 RESET Conditions RES reset during power-up RES reset during normal operation RES Wake-up HALT WDT time-out during normal operation WDT Wake-up HALT
OSC is selected). The system quits the HALT mode by an external reset, an interrupt, an external falling edge signal on port A, or a WDT overflow. An external reset causes device initialization, and the WDT overflow performs a warm reset. After examining the TO and PD flags, the reason for chip reset can be determined. The PD flag is cleared by system power-up or by executing the CLR WDT instruction, and is set by executing the HALT instruction. On the other hand, the TO flag is set if WDT time-out occurs, and causes a wake-up that only resets the PC (Program Counter) and SP, and leaves the others at their original state. The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit in port A can be independently selected to wake up the device by options. Awakening from an I/O port stimulus, the program resumes execution of the next instruction. On the other hand, awakening from an interrupt, two sequence may occur. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the program resumes execution at the next instruction. But if the interrupt is enabled, and the stack is not full, the regular interrupt response takes place. Rev. 1.30 18
Note: u stands for unchanged
V
DD
0 .0 1 m F * 100kW RES 10kW 0 .1 m F *
Reset Circuit Note: * Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise interference.
July 24, 2003
HT49R70A-1/HT49C70-1/HT49C70L
VDD RES S S T T im e - o u t C h ip R eset tS
ST
The functional unit chip reset status is shown below. PC Interrupt Prescaler, Divider Reset Timing Chart WDT, RTC, Time Base Timer/event Counter 000H Disabled Cleared Cleared. After master reset, WDT starts counting Off Input mode Points to the top of the stack
HALT W DT W DT T im e - o u t R eset E x te rn a l
W a rm
R eset
Input/output Ports SP Timer/Event Counter
RES SST 1 0 - b it R ip p le C o u n te r P o w e r - o n D e te c tio n
OSC1
C o ld R eset
Two timer/event counters are implemented in the device. One of them contains an 8-bit programmable count-up counter, the other contains a 16-bit programmable count-up counter. The Timer/Event Counter 0 clock source may come from the system clock or system clock/4 or RTC time-out signal or external source. System clock source or system clock/4 is selected by options. The Timer/Event Counter 1 clock source may come from TMR0 overflow or system clock or time base time-out signal or system clock/4 or external source, and the three former clock source is selected by options. Using external clock input allows the user to count exter-
Reset Configuration To guarantee that the system oscillator is started and stabilized, the SST (System Start-up Timer) provides an extra-delay of 1024 system clock pulses when the system awakes from a HALT state. Awaking from a HALT state, an SST delay is added. An extra option load time delay is added during reset and power on. The register states are summarized below: Register TMR0 TMR0C TMR1H TMR1L TMR1C Program Counter MP0 MP1 BP ACC TBLP TBLH STATUS INTC0 INTC1 RTCC PA PC Note: Reset (Power On) xxxx xxxx 0000 1--xxxx xxxx xxxx xxxx 0000 1--0000H xxxx xxxx xxxx xxxx ---- ---0 xxxx xxxx xxxx xxxx xxxx xxxx --00 xxxx -000 0000 -000 -000 --00 0111 1111 1111 1111 1111 * stands for warm reset u stands for unchanged x stands for unknown 19
WDT Time-out RES Reset (Norma Operation) (Normal Operation) xxxx xxxx 0000 1--xxxx xxxx xxxx xxxx 0000 1--0000H uuuu uuuu uuuu uuuu ---- ---0 uuuu uuuu uuuu uuuu uuuu uuuu --1u uuuu -000 0000 -000 -000 --00 0111 1111 1111 1111 1111 xxxx xxxx 0000 1--xxxx xxxx xxxx xxxx 0000 1--0000H uuuu uuuu uuuu uuuu ---- ---0 uuuu uuuu uuuu uuuu uuuu uuuu --uu uuuu -000 0000 -000 -000 --00 0111 1111 1111 1111 1111
RES Reset (HALT) xxxx xxxx 0000 1--xxxx xxxx xxxx xxxx 0000 1--0000H uuuu uuuu uuuu uuuu ---- ---0 uuuu uuuu uuuu uuuu uuuu uuuu --01 uuuu -000 0000 -000 -000 --00 0111 1111 1111 1111 1111
WDT Time-out (HALT)* uuuu uuuu uuuu u--uuuu uuuu uuuu uuuu uuuu u--0000H uuuu uuuu uuuu uuuu ---- ---u uuuu uuuu uuuu uuuu uuuu uuuu --11 uuuu -uuu uuuu -uuu -uuu --uu uuuu uuuu uuuu uuuu uuuu
Rev. 1.30
July 24, 2003
HT49R70A-1/HT49C70-1/HT49C70L
nal events, measure time internals or pulse widths, or generate an accurate time base. While using the internal clock allows the user to generate an accurate time base. There are two registers related to the Timer/Event Counter 0; TMR0 ([0DH]), TMR0C ([0EH]). Two physical registers are mapped to TMR0 location; writing TMR0 puts the starting value in the Timer/Event Counter 0 register and reading TMR0 takes the contents of the Timer/Event Counter 0. The TMR0C is a timer/event counter control register, which defines some options. There are three registers related to the Timer/Event Counter 1; TMR1H (0FH), TMR1L (10H), TMR1C (11H). Writing TMR1L will only put the written data to an internal lower-order byte buffer (8-bit) and writing TMR1H will transfer the specified data and the contents of the lower-order byte buffer to TMR1H and TMR1L registers, respectively. The Timer/Event Counter 1 preload register is changed by each writing TRM1H operations. Reading TMR1H will latch the contents of TMR1H and TMR1L counters to the destination and the lower-order byte buffer, respectively. Reading the tMR1L will read the contents of the lower-order byte buffer. The TMR1C is the Timer/Event Counter 1 control register, which deS y s te m S y s te m C lo c k C lo c k /4 RTC O ut TS TM R0 TE TM 1 TM 0 TON P u ls e W id th M e a s u re m e n t M o d e C o n tro l T im e r /E v e n t C c o u n te r 0 T P A 3 D a ta C T R L O v e r flo w to In te rru p t Q PFD0
fines the operating mode, counting enable or disable and an active edge. The TM0 and TM1 bits define the operation mode. The event count mode is used to count external events, which means that the clock source is from an external (TMR0, TMR1) pin. The timer mode functions as a normal timer with the clock source coming from the internal selected clock source. Finally, the pulse width measurement mode can be used to count the high or low level duration of the external signal (TMR0, TMR1), and the counting is based on the internal selected clock source. In the event count or timer mode, the timer/event counter starts counting at the current contents in the timer/event counter and ends at FFH (FFFFH). Once an overflow occurs, the counter is reloaded from the timer/event counter preload register, and generates an interrupt request flag (T0F; bit 6 of INTC0, T1F; bit 4 of INTC1). In the pulse width measurement mode with the values of the TON and TE bits equal to 1, after the TMR0 (TMR1) has received a transient from low to high (or high to low if the TE bit is 0), it will start counting until the TMR0 (TMR1) returns to the original level and resets the TON. The measured result remains in the timer/event counter
O p tio n U X
M
f IN
T
D a ta B u s TM 1 TM 0 T im e r /E v e n t C o u n te r 0 P r e lo a d R e g is te r R e lo a d
Timer/Event Counter 0 Label (TMR0C) 3/4 TE TON TS
Bits 0~2 3 4 5 Unused bit, read as 0
Function
Defines the TMR0 active edge of timer/event counter (0=active on low to high; 1=active on high to low) Enable/disable timer counting (0=disabled; 1=enabled) 2 to 1 multiplexer control inputs which selects the timer/event counter clock source (0=RTC outputs; 1= system clock or system clock/4) Defines the operating mode (TM1, TM0) 01= Event count mode (External clock) 10= Timer mode (Internal clock) 11= Pulse Width measurement mode (External clock) 00= Unused TMR0C Register
TM0 TM1
6 7
Rev. 1.30
20
July 24, 2003
HT49R70A-1/HT49C70-1/HT49C70L
even if the activated transient occurs again. In other words, only 1-cycle measurement can be made until the TON is set. The cycle measurement will re-function as long as it receives further transient pulse. In this operation mode, the timer/event counter begins counting not according to the logic level but to the transient edges. In the case of counter overflows, the counter is reloaded from the timer/event counter register and issues an interrupt request, as in the other two modes, i.e., event and timer modes. To enable the counting operation, the Timer ON bit (TON; bit 4 of TMR0C or TMR1C) should be set to 1. In the pulse width measurement mode, the TON is automatically cleared after the measurement cycle is completed. But in the other two modes, the TON can only be reset by instructions. The overflow of the Timer/Event Counter 0/1 is one of the wake-up sources and can also be applied to a PFD (Programmable Frequency Divider) output at PA3 by options. Only one PFD (PFD0 or PFD1) can be applied to PA3 by options . No matter what the operation mode is, writing a 0 to ET0I or ET1I disables the related interrupt service. When the PFD function is selected, executing CLR [PA].3 instruction to enable PFD output and executing SET [PA].3 instruction to disable PFD output.
T M R 0 O v e r flo w S y s te m C lo c k O p tio n S e le c t M U X D a ta b u s TS TM R1 TE TM 1 TM 0 TON P u ls e W id th M e a s u re m e n t M o d e C o n tro l T im e r /E v e n t C o u n te r 1 T P A 3 D a ta C T R L O v e r flo w T o In te rru p t Q PFD1 TM 1 TM 0 T im e r /E v e n t C o u n te r 1 P r e lo a d R e g is te r R e lo a d
In the case of timer/event counter OFF condition, writing data to the timer/event counter preload register also reloads that data to the timer/event counter. But if the timer/event counter is turn on, data written to the timer/event counter is kept only in the timer/event counter preload register. The timer/event counter still continues its operation until an overflow occurs. When the timer/event counter (reading TMR0/TMR1) is read, the clock is blocked to avoid errors, as this may results in a counting error. Blocking of the clock should be taken into account by the programmer. It is strongly recommended to load a desired value into the TMR0/TMR1 register first, before turning on the related timer/event counter, for proper operation since the initial value of TMR0/TMR1 is unknown. Due to the timer/event scheme, the programmer should pay special attention on the instruction to enable then disable the timer for the first time, whenever there is a need to use the timer/event function, to avoid unpredictable result. After this procedure, the timer/event function can be operated normally. An example is given, using one 8-bit and one 16-bit width Timer (timer 0; timer 1) cascaded into 24-bit width.
T im e B a s e O u t S y s te m C lo c k /4
Timer/Event Counter 1 Label (TMR1C) 3/4 TE TON TS
Bits 0~2 3 4 5 Unused bit, read as 0
Function
Defines the TMR1 active edge of the timer/event counter (0= active on low to high; 1= active on high to low) Enable/disable timer counting (0= disabled; 1= enabled) 2 to 1 multiplexer control inputs to select the timer/event counter clock source (0= option clock source; 1= system clock/4) Defines the operating mode 01= Event count mode (External clock) 10= Timer mode (Internal clock) 11= Pulse Width measurement mode (External clock) 00= Unused TMR1C Register
TM1 TM0
7 6
Rev. 1.30
21
July 24, 2003
HT49R70A-1/HT49C70-1/HT49C70L
START: mov mov mov mov mov mov mov mov set clr mov mov mov mov mov set set END a,09h intc0,a a,01h intc1, a a, 80h tmr1c,a a, 0a0h tmr0c, a tmr1c.4 tmr1c.4 a, 00h tmr0, a a, 00h tmr1l, a tmr1h, a tmr0c.4 tmr1c.4; ; Set ET0I&EMI bits to ; enable timer 0 and global interrupt ; Set ET1I bit to enable ; timer 1 interrupt ; Set operating mode as ; timer mode and select mask option clock source ; Set operating mode as timer ; mode and select system Clock/4 ; Enable then disable timer 1 ; for the first time ; Load a desired value into ; the TMR0/TMR1 register ; ; ; ; Normal operation
Input/Output Ports There are two 8-bit bidirectional input/output ports, PA and PC and one 8-bit input port PB. PA, PB and PC are mapped to [12H], [14H] and [16H] of the RAM, respectively. PA0~PA3 can be configured as CMOS (output) or NMOS (input/output) with or without pull-high resistor by options. PA4~PA7 are always pull-high and NMOS (input/output). If NMOS (input) is chosen, each bit on the port (PA0~PA7) can be configured as a wake-up input. PB can only be used for input operation. PC can be configured as CMOS output or NMOS input/output with or without pull-high resistor by options. All the ports for the input operation (PA, PB and PC), are non-latched, that is, the inputs should be ready at the T2 rising edge of the instruction MOV A, [m]" (m=12H or 14H or 16H). For PA, PC output operation, all data are latched and remain unchanged until the output latch is rewritten. When the PA and PC structures are open drain NMOS type, it should be noted that, before reading data from the pads, a 1 should be written to the related bits to disable the NMOS device. That is, executing first the instruction SET [m].i (i=0~7 for PA) to disable related NMOS device, and then MOV A, [m] to get stable data. After chip reset, these input lines remain at the high level or are left floating (by options). Each bit of these output latches can be set or cleared by the MOV [m], A (m=12H or 16H) instruction. Some instructions first input data and then follow the output operations. For example, SET [m].i, CLR [m].i, CPL [m], CPLA [m] read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the
latches or to the accumulator. When a PA or PC line is used as an I/O line, the related PA or PC line options should be configured as NMOS with or without pull-high resistor. Once a PA or PC line is selected as a CMOS output, the I/O function cannot be used. The input state of a PA or PC line is read from the related PA or PC pad. When the PA or PC is configured as NMOS with or without pull-high resistor, one should be careful when applying a read-modify-write instruction to PA or PC. Since the read-modify-write will read the entire port state (pads state) first, execute the specified instruction and then write the result to the port data register. When the read operation is executed, a fault pad state (caused by the load effect or floating state) may be read. Errors will then occur. There are three function pins that share with the PA port: PA0/BZ, PA1/BZ and PA3/PFD. The BZ and BZ are buzzer driving output pair and the PFD is a programmable frequency divider output. If the user wants to use the BZ/BZ or PFD function, the related PA port should be set as a CMOS output. The buzzer output signals are controlled by PA0 and PA1 data registers as defined in the following table. PA1 Data Register 0 1 X PA0 Data Register 0 0 1 PA0/PA1 Pad State PA0=BZ, PA1=BZ PA0=BZ, PA1=0 PA0=0, PA1=0
Note: X stands for unused
Rev. 1.30
22
July 24, 2003
HT49R70A-1/HT49C70-1/HT49C70L
V V
DD DD
W eak P u ll- u p O p tio n (P A 0 ~ P A 3 , P C ) V PA0~PA7 PC 0~PC 7
D a ta B u s W r ite C h ip R e s e t
D CK S Q
Q
C /N O (P P
MOS p tio n A0~PA3, C)
DD
W eak P u ll- u p
D a ta b u s R e a d I/O
PB0~PB7
Re S Wa (P A
ad ys ke o
I/O te m -u p n ly )
O p tio n
Input/Output Ports The PFD output signal function is controlled by the PA3 data register and the timer/event counter state. The PFD output signal frequency is also dependent on the timer/event counter overflow period. The definitions of PFD control signal and PFD output frequency are listed in the following table. Timer PA3 Data PA3 Pad PFD Timer Preload Register State Frequency Value OFF OFF ON ON Note: X X N N 0 1 0 1 U 0 PFD 0 X X fINT/ [2(256-N)] X
PB input Ports LCD Display Memory The device provides an area of embedded data memory for LCD display. This area is located from 40H to 68H of the RAM at Bank 1. Bank pointer (BP; located at 04H of the RAM) is the switch between the RAM and the LCD display memory. When the BP is set as 01H, any data written into 40H~68H will affect the LCD display. When the BP is cleared to 00H, any data written into 40H~68H is meant to access the general purpose data memory. The LCD display memory can be read and written to only by indirect addressing mode using MP1. When data is written into the display data area, it is automatically read by the LCD driver which then generates the corresponding LCD driving signals. To turn the display on or off, a 1 or a 0 is written to the corresponding bit of the display memory, respectively. The figure illustrates the mapping between the display memory and LCD pattern for the device.
X stands for unused U stands for unknown 256 is for TMR0. If TMR1 is used to generate PFD, the number should be 65536.
COM 0 1
40H
41H
42H
43H
66
67
68
B it 0 1
2 2 3 3
SEGMENT
0
1
2
3
38
39
40
Display Memory
Rev. 1.30
23
July 24, 2003
HT49R70A-1/HT49C70-1/HT49C70L
LCD Driver Output The output number of the LCD driver device can be 412, 413 or 404 by option (i.e., 1/2 duty, 1/3 duty or 1/4 duty). The bias type LCD driver can be R type or C type for HT49R70A-1/HT49C70-1 while the bias type LCD driver can only be C type for HT49C70L. If the R bias type is selected, no external capacitor is required. If the C bias type is selected, a capacitor mounted between C1 and C2 pins is needed. The LCD driver bias voltage for HT49R70A-1/HT49C70-1 can be 1/2 bias or 1/3 bias by option, while the LCD driver bias voltage for HT49C70L can only be 1/2 bias. If 1/2 bias is selected, a capacitor mounted between V2 pin and ground is required. If 1/3 bias is selected, two capacitors are needed for V1 and V2 pins.
D u r in g a r e s e t p u ls e C O M 0 ,C O M 1 ,C O M 2 A ll L C D d r iv e r o u tp u ts N o r m a l o p e r a tio n m o d e VA VB VSS VA VB VSS
LCD bias power supply selection for HT49R70A-1/ HT49C70-1: There are two types of selections: 1/2 bias or 1/3 bias. LCD bias type selection for HT49R70A-1/HT49C70-1: This option is to determine what kind of bias is selected, R type or C type. Low Voltage Reset/Detector Functions There is a low voltage detector (LVD) and a low voltage reset circuit (LVR) implemented in the microcontroller. These two functions can be enabled/disabled by options. Once the options of LVD is enabled, the user can use the RTCC.3 to enable/disable (1/0) the LVD circuit and read the LVD detector status (0/1) from RTCC.5; otherwise, the LVD function is disabled.
*
COM0 COM1 CO M 2* L C D s e g m e n ts O N C O M 0 ,1 ,2 s id e s a r e u n lig h te d O n ly L C D s e g m e n ts O N C O M 0 s id e a r e lig h te d O n ly L C D s e g m e n ts O N C O M 1 s id e a r e lig h te d O n ly L C D s e g m e n ts O N C O M 2 s id e a r e lig h te d L C D s e g m e n ts O N C O M 0 ,1 s id e s a r e lig h te d s e g m e n ts O N C O M 0 , 2 s id e s a r e lig h te d L C D s e g m e n ts O N C O M 1 ,2 s id e s a r e lig h te d L C D s e g m e n ts O N C O M 0 ,1 ,2 s id e s a r e lig h te d HALT M ode C O M 0 ,C O M 1 ,C O M 2 * A ll L C D d r iv e r o u tp u ts LCD
*
*
VB VS VA VB VS VA VB VS VA VB VS VA VB VS VA VB VS VA VB VS VA VB VS VA VB VS VA VB VS VA VB VS S S S S S S
VA
S S S S S
VA VB VSS VA VB VSS
N o te :
" * " O m it th e C O M 2 s ig n a l, if th e 1 /2 d u ty L C D is u s e d . V A = V L C D , V B = 1 /2 V L C D fo r H T 4 9 R 7 0 A -1 /H T 4 9 C 7 0 -1 V A = 2 V 2 , V B = V 2 , C ty p e fo r H T 4 9 C 7 0 L
LCD Driver Output (1/3 Duty, 1/2 Bias, R/C Type)
Rev. 1.30
24
July 24, 2003
HT49R70A-1/HT49C70-1/HT49C70L
VA VB VC VSS VA VB VC COM1 VSS VA VB VC COM2 VSS VA VB COM3 VC VSS VA VB L C D s e g m e n ts O N C O M 2 s id e lig h te d VC VSS
COM0
N o te : 1 /4 d u ty , 1 /3 b ia s , C ty p e : " V A " 3 /2 V L C D , " V B " V L C D , " V C " 1 /2 V L C D 1 /4 d u ty , 1 /3 b ia s , R ty p e : " V A " V L C D , " V B " 2 /3 V L C D , " V C " 1 /3 V L C D 1 /3 b ia s o n ly fo r H T 4 9 R 7 0 A - 1 /H T 4 9 C 7 0 - 1
LCD Driver Output The LVR has the same effect or function with the external RES signal which performs chip reset. During HALT state, LVR is disabled. The RTCC register definitions are listed in the table on the next page. Register Bit No. 0~2 3 RTCC (09H) 4 5 6, 7 Label RT0~RT2 LVDC* QOSC LVDO* 3/4 Read/Write Reset R/W R/W R/W R 3/4 111B 0 0 0 3/4 Function 8 to 1 multiplexer control inputs to select the real clock prescaler output LVD enable/disable (1/0) 32768Hz OSC quick start-up oscillation 0/1: quickly/slowly start LVD detection output (1/0) 1: low voltage detected Unused bit, read as 0
Note: * For HT49R70A-1/HT49C70-1
Rev. 1.30
25
July 24, 2003
HT49R70A-1/HT49C70-1/HT49C70L
Options The following shows the options in the device. All these options should be defined in order to ensure proper functioning system. Options OSC type selection. This option is to determine whether an RC or crystal or 32768Hz crystal oscillator is chosen as system clock. WDT Clock source selection. RTC and Time Base. There are three types of selections: system clock/4 or RTC OSC or WDT OSC. WDT enable/disable selection. WDT can be enabled or disabled by options. CLR WDT times selection. This option defines the method to clear the WDT by instruction. One time means that the CLR WDT can clear the WDT. Two times means that if both of the CLR WDT1 and CLR WDT2 have been executed, only then will the WDT be cleared. Time Base time-out period selection. The Time Base time-out period ranges from clock/212 to clock/215 Clock means the clock source selected by options. Buzzer output frequency selection. There are eight types of frequency signals for buzzer output: Clock/22~Clock/29. Clock means the clock source selected by options. Wake-up selection. This option defines the wake-up capability. External I/O pins (PA only) all have the capability to wake-up the chip from a HALT by a falling edge. Pull-high selection. This option is to decide whether the pull-high resistance is visible or not on the PA0~PA3 and PC. (PB and PA4~PA7 are always pull-high) PA0~PA3 and PC0~PC7 CMOS or NMOS selection. The structure of PA0~PA3 and PC0~PC7 can be selected as CMOS or NMOS individually. When the CMOS is selected, the related pins only can be used for output operations. When the NMOS is selected, the related pins can be used for input or output operations. (PA4~PA7 are always NMOS) Clock source selection of Timer/Event Counter 0. There are two types of selections: system clock or system clock/4. Clock source selection of Timer/Event Counter 1. There are three types of selections: TMR0 overflow, system clock or Time Base overflow. I/O pins share with other function selections. PA0/BZ, PA1/BZ: PA0 and PA1 can be set as I/O pins or buzzer outputs. PA3/PFD: PA3 can be set as I/O pins or PFD output. LCD common selection. There are three types of selections: 2 common (1/2 duty) or 3 common (1/3 duty) or 4 common (1/4 duty). If the 4 common is selected, the segment output pin SEG40 will be set as a common output. LCD bias power supply selection There are two types of selections: 1/2 bias or 1/3 bias for HT49R70A-1/HT49C70-1. LCD bias type selection This option is to determine what kind of bias is selected, R type or C type for HT49R70A-1/HT49C70-1. LCD driver clock selection. There are seven types of frequency signals for the LCD driver circuits: fS/22~fS/28. fS stands for the clock source selection by options. LCD ON/OFF at HALT selection LVR selection. LVR has enable or disable options LVD selection. LVD has enable or disable options PFD selection If PA3 is set as PFD output, there are two types of selections; One is PFD0 as the PFD output, the other is PFD1 as the PFD output. PFD0, PFD1 are the timer overflow signals of the Timer/Event Counter 0, Timer/Event Counter 1 respectively.
Rev. 1.30
26
July 24, 2003
HT49R70A-1/HT49C70-1/HT49C70L
Application Circuits
RC Oscillator Application
V 470pF 24kW ~ 1M W V
DD DD
Crystal Oscillator Application
LCD Panel
C1 OSC1 C2 CO M 0~CO M 3 SEG 0~SEG 39 LCD Panel
CO M 0~CO M 3 SEG 0~SEG 39 OSC1 VLCD C1 C2
LC D Pow er S u p p ly 0 .1 m F
OSC2
VLCD C1 C2
LC D Pow er S u p p ly 0 .1 m F
fS
YS
/4
OSC2 OSC3
V1
0 .1 m F
OSC3
V1
0 .1 m F
V2 OSC4
OSC4
0 .1 m F
V2
0 .1 m F
V
DD
PA0~PA7
0 .0 1 m F *
V
DD
PA0~PA7
0 .0 1 m F *
PB0~PB7 PC 0~PC 7
RES
PB0~PB7 PC 0~PC 7 RES IN T 0 IN T 1 TM R0 TM R1
100kW
IN T 0 IN T 1 TM R0 TM R1
100kW
10kW 0 .1 m F *
10kW 0 .1 m F *
H T 4 9 R 7 0 A -1 /H T 4 9 C 7 0 -1
H T 4 9 R 7 0 A -1 /H T 4 9 C 7 0 -1
32768Hz Crystal Oscillator Application
OSC1 OSC2 OSC3 VLCD C1 C2 V
DD
CO M 0~CO M 3 SEG 0~SEG 39
LCD Panel
LC D Pow er S u p p ly 0 .1 m F
OSC4
V1
0 .0 1 m F *
0 .1 m F
100kW RES 10kW 0 .1 m F *
V2
0 .1 m F
IN T 0 IN T 1 TM R0 TM R1
PA0~PA7 PB0~PB7 PC 0~PC 7
H T 4 9 R 7 0 A -1 /H T 4 9 C 7 0 -1
Note:
C1=C2=300pF if fSYS < 1MHz, Otherwise, C1=C2=0 The resistance and capacitance for reset circuit should be designed in such a way as to ensure that the VDD is stable and remains within a valid operating voltage range before bringing RES to high. * Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise interference.
Rev. 1.30
27
July 24, 2003
HT49R70A-1/HT49C70-1/HT49C70L
RC Oscillator Application
V 470pF 560kW ~ 1M W OSC1
DD
Crystal Oscillator Application
CO M 0~CO M 3 SEG 0~SEG 39 LCD Panel
200pF OSC1 200pF
CO M 0~CO M 3 SEG 0~SEG 39
LCD Panel
VLCD V
0 .1 m F
OSC2
VLCD
0 .1 m F
DD
C1 fS /4 OSC2 OSC3 V2 PA0~PA7 V
100kW RES 0 .1 m F
0 .1 m F
C1 OSC3 C2 V1 OSC4 V2 V PA0~PA7 V
100kW RES 0 .1 m F
DD
0 .1 m F
YS
C2 V1 0 .1 m F
0 .1 m F
OSC4
V
DD
DD
PB0~PB7
DD
PB0~PB7 PC 0~PC 7 IN T 0 IN T 1 TM R0 TM R1
PC 0~PC 7 IN T 0 IN T 1 TM R0 TM R1
H T49C 70L
H T49C 70L
32768Hz Crystal Oscillator Application
OSC1 OSC2 OSC3 VLCD CO M 0~CO M 3 SEG 0~SEG 39 LCD Panel
0 .1 m F
OSC4 V
100kW RES 0 .1 m F
DD
C1 C2 V1
0 .1 m F
0 .1 m F
V2 IN T 0 IN T 1 TM R0 TM R1 PA0~PA7 PB0~PB7 PC 0~PC 7
V
DD
H T49C 70L
Note:
The resistance and capacitance for reset circuit should be designed in such a way as to ensure that the VDD is stable and remains within a valid operating voltage range before bringing RES to high.
Rev. 1.30
28
July 24, 2003
HT49R70A-1/HT49C70-1/HT49C70L
Instruction Set Summary
Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Add data memory to ACC Add ACC to data memory Add immediate data to ACC Add data memory to ACC with carry Add ACC to data memory with carry Subtract immediate data from ACC Subtract data memory from ACC Subtract data memory from ACC with result in data memory Subtract data memory from ACC with carry Subtract data memory from ACC with carry and result in data memory Decimal adjust ACC for addition with result in data memory 1 1(1) 1 1 1(1) 1 1 1(1) 1 1(1) 1(1) Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV C Description Instruction Cycle Flag Affected
Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] AND data memory to ACC OR data memory to ACC Exclusive-OR data memory to ACC AND ACC to data memory OR ACC to data memory Exclusive-OR ACC to data memory AND immediate data to ACC OR immediate data to ACC Exclusive-OR immediate data to ACC Complement data memory Complement data memory with result in ACC 1 1 1 1(1) 1(1) 1(1) 1 1 1 1(1) 1 Z Z Z Z Z Z Z Z Z Z Z
Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Clear bit of data memory Set bit of data memory 1(1) 1(1) None None Move data memory to ACC Move ACC to data memory Move immediate data to ACC 1 1(1) 1 None None None Rotate data memory right with result in ACC Rotate data memory right Rotate data memory right through carry with result in ACC Rotate data memory right through carry Rotate data memory left with result in ACC Rotate data memory left Rotate data memory left through carry with result in ACC Rotate data memory left through carry 1 1(1) 1 1(1) 1 1(1) 1 1(1) None None C C None None C C Increment data memory with result in ACC Increment data memory Decrement data memory with result in ACC Decrement data memory 1 1(1) 1 1(1) Z Z Z Z
Rev. 1.30
29
July 24, 2003
HT49R70A-1/HT49C70-1/HT49C70L
Mnemonic Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT No operation Clear data memory Set data memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of data memory Swap nibbles of data memory with result in ACC Enter power down mode Note: x: Immediate data m: Data memory address A: Accumulator i: 0~7 number of bits addr: Program memory address O: Flag is affected -: Flag is not affected
(1)
Description
Instruction Cycle
Flag Affected
Jump unconditionally Skip if data memory is zero Skip if data memory is zero with data movement to ACC Skip if bit i of data memory is zero Skip if bit i of data memory is not zero Skip if increment data memory is zero Skip if decrement data memory is zero Skip if increment data memory is zero with result in ACC Skip if decrement data memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt
2 1(2) 1(2) 1(2) 1(2) 1(3) 1(3) 1(2) 1(2) 2 2 2 2
None None None None None None None None None None None None None
Read ROM code (current page) to data memory and TBLH Read ROM code (last page) to data memory and TBLH
2(1) 2(1)
None None
1 1(1) 1(1) 1 1 1 1(1) 1 1
None None None TO,PD TO(4),PD(4) TO(4),PD(4) None None TO,PD
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). : If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). Otherwise the original instruction cycle is unchanged. : and (2) : The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PD are cleared. Otherwise the TO and PD flags remain unchanged.
(2)
(3) (1) (4)
Rev. 1.30
30
July 24, 2003
HT49R70A-1/HT49C70-1/HT49C70L
Instruction Definition
ADC A,[m] Description Operation Affected flag(s) TC2 3/4 ADCM A,[m] Description Operation Affected flag(s) TC2 3/4 ADD A,[m] Description Operation Affected flag(s) TC2 3/4 ADD A,x Description Operation Affected flag(s) TC2 3/4 ADDM A,[m] Description Operation Affected flag(s) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O Add data memory and carry to the accumulator The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator. ACC ACC+[m]+C
Add the accumulator and carry to data memory The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory. [m] ACC+[m]+C
Add data memory to the accumulator The contents of the specified data memory and the accumulator are added. The result is stored in the accumulator. ACC ACC+[m]
Add immediate data to the accumulator The contents of the accumulator and the specified data are added, leaving the result in the accumulator. ACC ACC+x
Add the accumulator to the data memory The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. [m] ACC+[m]
Rev. 1.30
31
July 24, 2003
HT49R70A-1/HT49C70-1/HT49C70L
AND A,[m] Description Operation Affected flag(s) TC2 3/4 AND A,x Description Operation Affected flag(s) TC2 3/4 ANDM A,[m] Description Operation Affected flag(s) TC2 3/4 CALL addr Description TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical AND accumulator with data memory Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND [m]
Logical AND immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND x
Logical AND data memory with the accumulator Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory. [m] ACC AND [m]
Subroutine call The instruction unconditionally calls a subroutine located at the indicated address. The program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. The indicated address is then loaded. Program execution continues with the instruction at this address. Stack PC+1 PC addr TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation
Affected flag(s)
CLR [m] Description Operation Affected flag(s)
Clear data memory The contents of the specified data memory are cleared to 0. [m] 00H TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Rev. 1.30
32
July 24, 2003
HT49R70A-1/HT49C70-1/HT49C70L
CLR [m].i Description Operation Affected flag(s) TC2 3/4 CLR WDT Description Operation TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Clear bit of data memory The bit i of the specified data memory is cleared to 0. [m].i 0
Clear Watchdog Timer The WDT is cleared (clears the WDT). The power down bit (PD) and time-out bit (TO) are cleared. WDT 00H PD and TO 0 TC2 3/4 TC1 3/4 TO 0 PD 0 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
CLR WDT1 Description
Preclear Watchdog Timer Together with CLR WDT2, clears the WDT. PD and TO are also cleared. Only execution of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PD flags remain unchanged. WDT 00H* PD and TO 0* TC2 3/4 TC1 3/4 TO 0* PD 0* OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation
Affected flag(s)
CLR WDT2 Description
Preclear Watchdog Timer Together with CLR WDT1, clears the WDT. PD and TO are also cleared. Only execution of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PD flags remain unchanged. WDT 00H* PD and TO 0* TC2 3/4 TC1 3/4 TO 0* PD 0* OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation
Affected flag(s)
CPL [m] Description Operation Affected flag(s)
Complement data memory Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. [m] [m] TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4
Rev. 1.30
33
July 24, 2003
HT49R70A-1/HT49C70-1/HT49C70L
CPLA [m] Description Complement data memory and place result in the accumulator Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. The complemented result is stored in the accumulator and the contents of the data memory remain unchanged. ACC [m] TC2 3/4 DAA [m] Description TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4
Operation Affected flag(s)
Decimal-Adjust accumulator for addition The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored in the data memory and only the carry flag (C) may be affected. If ACC.3~ACC.0 >9 or AC=1 then [m].3~[m].0 (ACC.3~ACC.0)+6, AC1=AC else [m].3~[m].0 (ACC.3~ACC.0), AC1=0 and If ACC.7~ACC.4+AC1 >9 or C=1 then [m].7~[m].4 ACC.7~ACC.4+6+AC1,C=1 else [m].7~[m].4 ACC.7~ACC.4+AC1,C=C TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Operation
Affected flag(s)
DEC [m] Description Operation Affected flag(s)
Decrement data memory Data in the specified data memory is decremented by 1. [m] [m]-1 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4
DECA [m] Description Operation Affected flag(s)
Decrement data memory and place result in the accumulator Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]-1 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4
Rev. 1.30
34
July 24, 2003
HT49R70A-1/HT49C70-1/HT49C70L
HALT Description Enter power down mode This instruction stops program execution and turns off the system clock. The contents of the RAM and registers are retained. The WDT and prescaler are cleared. The power down bit (PD) is set and the WDT time-out bit (TO) is cleared. PC PC+1 PD 1 TO 0 TC2 3/4 INC [m] Description Operation Affected flag(s) TC2 3/4 INCA [m] Description Operation Affected flag(s) TC2 3/4 JMP addr Description Operation Affected flag(s) TC2 3/4 MOV A,[m] Description Operation Affected flag(s) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 0 PD 1 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation
Affected flag(s)
Increment data memory Data in the specified data memory is incremented by 1 [m] [m]+1
Increment data memory and place result in the accumulator Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]+1
Directly jump The program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. PC addr
Move data memory to the accumulator The contents of the specified data memory are copied to the accumulator. ACC [m]
Rev. 1.30
35
July 24, 2003
HT49R70A-1/HT49C70-1/HT49C70L
MOV A,x Description Operation Affected flag(s) TC2 3/4 MOV [m],A Description Operation Affected flag(s) TC2 3/4 NOP Description Operation Affected flag(s) TC2 3/4 OR A,[m] Description Operation Affected flag(s) TC2 3/4 OR A,x Description Operation Affected flag(s) TC2 3/4 ORM A,[m] Description Operation Affected flag(s) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Move immediate data to the accumulator The 8-bit data specified by the code is loaded into the accumulator. ACC x
Move the accumulator to data memory The contents of the accumulator are copied to the specified data memory (one of the data memories). [m] ACC
No operation No operation is performed. Execution continues with the next instruction. PC PC+1
Logical OR accumulator with data memory Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR [m]
Logical OR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR x
Logical OR data memory with the accumulator Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. [m] ACC OR [m]
Rev. 1.30
36
July 24, 2003
HT49R70A-1/HT49C70-1/HT49C70L
RET Description Operation Affected flag(s) TC2 3/4 RET A,x Description Operation TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Return from subroutine The program counter is restored from the stack. This is a 2-cycle instruction. PC Stack
Return and place immediate data in the accumulator The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data. PC Stack ACC x TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
RETI Description Operation
Return from interrupt The program counter is restored from the stack, and interrupts are enabled by setting the EMI bit. EMI is the enable master (global) interrupt bit. PC Stack EMI 1 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
RL [m] Description Operation
Rotate data memory left The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 [m].7 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
RLA [m] Description Operation
Rotate data memory left and place result in the accumulator Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 [m].7 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
Rev. 1.30
37
July 24, 2003
HT49R70A-1/HT49C70-1/HT49C70L
RLC [m] Description Operation Rotate data memory left through carry The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 C C [m].7 TC2 3/4 RLCA [m] Description TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Affected flag(s)
Rotate left through carry and place result in the accumulator Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored in the accumulator but the contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 C C [m].7 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Operation
Affected flag(s)
RR [m] Description Operation
Rotate data memory right The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 [m].0 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
RRA [m] Description Operation
Rotate right and place result in the accumulator Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i) [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 [m].0 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
RRC [m] Description Operation
Rotate data memory right through carry The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 C C [m].0 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Affected flag(s)
Rev. 1.30
38
July 24, 2003
HT49R70A-1/HT49C70-1/HT49C70L
RRCA [m] Description Rotate right through carry and place result in the accumulator Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is stored in the accumulator. The contents of the data memory remain unchanged. ACC.i [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 C C [m].0 TC2 3/4 SBC A,[m] Description Operation Affected flag(s) TC2 3/4 SBCM A,[m] Description Operation Affected flag(s) TC2 3/4 SDZ [m] Description TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Operation
Affected flag(s)
Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator. ACC ACC+[m]+C
Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory. [m] ACC+[m]+C
Skip if decrement data memory is 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, [m] ([m]-1) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
SDZA [m] Description
Decrement data memory and place result in ACC, skip if 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. The result is stored in the accumulator but the data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, ACC ([m]-1) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
Rev. 1.30
39
July 24, 2003
HT49R70A-1/HT49C70-1/HT49C70L
SET [m] Description Operation Affected flag(s) TC2 3/4 SET [m]. i Description Operation Affected flag(s) TC2 3/4 SIZ [m] Description TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Set data memory Each bit of the specified data memory is set to 1. [m] FFH
Set bit of data memory Bit i of the specified data memory is set to 1. [m].i 1
Skip if increment data memory is 0 The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, [m] ([m]+1) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
SIZA [m] Description
Increment data memory and place result in ACC, skip if 0 The contents of the specified data memory are incremented by 1. If the result is 0, the next instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, ACC ([m]+1) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
SNZ [m].i Description
Skip if bit i of the data memory is not 0 If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i0
Operation Affected flag(s)
TC2 3/4
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Rev. 1.30
40
July 24, 2003
HT49R70A-1/HT49C70-1/HT49C70L
SUB A,[m] Description Operation Affected flag(s) TC2 3/4 SUBM A,[m] Description Operation Affected flag(s) TC2 3/4 SUB A,x Description Operation Affected flag(s) TC2 3/4 SWAP [m] Description Operation Affected flag(s) TC2 3/4 SWAPA [m] Description Operation TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+[m]+1
Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. [m] ACC+[m]+1
Subtract immediate data from the accumulator The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+x+1
Swap nibbles within the data memory The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged. [m].3~[m].0 [m].7~[m].4
Swap data memory and place result in the accumulator The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged. ACC.3~ACC.0 [m].7~[m].4 ACC.7~ACC.4 [m].3~[m].0 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
Rev. 1.30
41
July 24, 2003
HT49R70A-1/HT49C70-1/HT49C70L
SZ [m] Description Skip if data memory is 0 If the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0
Operation Affected flag(s)
TC2 3/4 SZA [m] Description
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move data memory to ACC, skip if 0 The contents of the specified data memory are copied to the accumulator. If the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0
Operation Affected flag(s)
TC2 3/4 SZ [m].i Description
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Skip if bit i of the data memory is 0 If bit i of the specified data memory is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i=0
Operation Affected flag(s)
TC2 3/4 TABRDC [m] Description Operation
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move the ROM code (current page) to TBLH and data memory The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved to the specified data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
TABRDL [m] Description Operation
Move the ROM code (last page) to TBLH and data memory The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
Rev. 1.30
42
July 24, 2003
HT49R70A-1/HT49C70-1/HT49C70L
XOR A,[m] Description Operation Affected flag(s) TC2 3/4 XORM A,[m] Description Operation Affected flag(s) TC2 3/4 XOR A,x Description Operation Affected flag(s) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical XOR accumulator with data memory Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator. ACC ACC XOR [m]
Logical XOR data memory with the accumulator Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected. [m] ACC XOR [m]
Logical XOR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected. ACC ACC XOR x
Rev. 1.30
43
July 24, 2003
HT49R70A-1/HT49C70-1/HT49C70L
Package Information
100-pin QFP (1420) Outline Dimensions
C D 80 51 G H
I 81 50
F A B
E
100
31 K 1 30 a J
Symbol A B C D E F G H I J K a
Dimensions in mm Min. 18.50 13.90 24.50 19.90 3/4 3/4 2.50 3/4 3/4 1 0.10 0 Nom. 3/4 3/4 3/4 3/4 0.65 0.30 3/4 3/4 0.10 3/4 3/4 3/4 Max. 19.20 14.10 25.20 20.10 3/4 3/4 3.10 3.40 3/4 1.40 0.20 7
Rev. 1.30
44
July 24, 2003
HT49R70A-1/HT49C70-1/HT49C70L
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Sales Office) 11F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan Tel: 886-2-2782-9635 Fax: 886-2-2782-9636 Fax: 886-2-2782-7128 (International sales hotline) Holtek Semiconductor (Shanghai) Inc. 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holtek Semiconductor (Hong Kong) Ltd. Block A, 3/F, Tin On Industrial Building, 777-779 Cheung Sha Wan Rd., Kowloon, Hong Kong Tel: 852-2-745-8288 Fax: 852-2-742-8657 Holmate Semiconductor, Inc. 46712 Fremont Blvd., Fremont, CA 94538 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com Copyright O 2003 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.30
45
July 24, 2003

▲Up To Search▲

Price & Availability of HT49R70A-1

	To Download HT49R70A-1 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .